The optimization of database systems is an important part of database research. Database users demand a high query throughput and low query latency, which is challenging because the data amounts being stored are growing continuously. One promising way to improve the query processing performance is to build specialized processors that are tailor made for database query processing. Such processors provide a high performance and besides exhibit low power consumption. The key idea is to (1) avoid unnecessary instructions, (2) build tailor-made instructions, and (3) optimize the overall processor design. Removing unnecessary instructions, e.g., multimedia instructions that are not or are rarely required, frees chip space, which can be used to increase the core count and thus the performance of the processor. Contrary, specialized instructions can significantly reduce the time for heavily used operations (e.g., join, aggregation, sorting) at the cost of reasonable increased chip space. The new instructions could either allow processing of native database data types like SQL decimal, combine instructions that are often executed together (e.g., shift and mask), inherently include parallelism like SIMD for certain operations, or even allow operations that had previously emulated costly with many instructions (e.g. bit permutations). Similarly, optimizing the overall processor design allows query performance. Database operations have typically a low arithmetic complexity and therefore greatly benefit of wide buses between the cores and memory. Similar effects can be achieved by choosing a suitable topology for connecting the cores. Certain processor features like cache coherence, however, might not be required for a database system and can be removed to allow superior processor designs at the cost of more complex algorithms. Summarizing, the aim of the topic is to (1) identify performance hot spots in query processing, (2) develop processor instructions or extensions that are tailor-made for query processing, (3) optimize the processor design, and (4) develop new algorithms that exploit the new instructions and are adapted to the novel processor design.

Main Advisor at Technische Universität Dresden (TUD)
Co-advisor at Poznan University of Technology (PUT)